forming trenches in a semiconductor substrate that define active regions therebetween;

forming a device isolation film that fills the trenches in the substrate;

forming a tunnel insulating film on the active regions of the substrate;

forming a plurality of floating gates each on the tunnel insulating film over the active regions of the substrate;

removing a portion of the device isolation film over the trenches in the substrate to expose sidewalls of the floating gates;

recessing a region of the device isolation film in the trenches so that the recessed region has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches and so that an edge of the recessed region is aligned with a sidewall of an adjacent gate, wherein the floating gate is formed wider than the active region of the substrate and an edge portion of the floating gate partially overlaps a portion of the device isolation film in the trench;

forming an inter-gate dielectric film extending across the floating gates and the device isolation film; and

forming a control gate conductive film on the inter-gate dielectric film and extending across the floating gates.