| US 7,510,932 B2 | ||
| Semiconductor devices having a field effect transistor and methods of fabricating the same | ||
| Chang-Woo Oh, Gyeonggi-do (Korea, Republic of); Dong-Gun Park, Gyeonggi-do (Korea, Republic of); Dong-Won Kim, Gyeonggi-do (Korea, Republic of); and Jeong-Dong Choe, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to SAms Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Jun. 18, 2007, as Appl. No. 11/764,751. | ||
| Application 11/764751 is a division of application No. 11/090740, filed on Mar. 24, 2005, granted, now 7,247,896. | ||
| Claims priority of application No. 2004-24599 (KR), filed on Apr. 09, 2004. | ||
| Prior Publication US 2008/0032469 A1, Feb. 07, 2008 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—257 [438/258; 438/311; 438/933; 257/E21.004; 257/E21.17; 257/E21.102; 257/E21.207; 257/E21.135] | 19 Claims |
| 1. A method of forming a semiconductor device, comprising:
sequentially stacking a support pattern and a device active pattern on a substrate;
doping a portion of the support pattern;
forming a gate electrode crossing over the device active pattern, being interposed by a gate insulation layer, said gate electrode
being disposed on the doped portion of the support pattern;
forming an undercut region by removing a non-doped portion of the support pattern;
forming a filling insulation pattern in the undercut region; and
forming a source/drain region in the device active pattern at both sides of the gate electrode,
wherein the device active pattern under the gate electrode is formed of a strained silicon having a lattice width wider than
a silicon lattice width.
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