| US 7,510,924 B2 | ||
| Method for manufacturing memory cell | ||
| Tzu-Hsuan Hsu, Hsinchu (Taiwan); Erh-Kun Lai, Hsinchu (Taiwan); Hang-Ting Lue, Hsinchu (Taiwan); and Chia-Hua Ho, Hsinchu (Taiwan) | ||
| Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan) | ||
| Filed on Aug. 09, 2007, as Appl. No. 11/836,142. | ||
| Application 11/836142 is a division of application No. 11/162274, filed on Sep. 05, 2005, granted, now 7,268,379. | ||
| Prior Publication US 2008/0002477 A1, Jan. 03, 2008 | ||
| Int. Cl. H01L 21/337 (2006.01) | ||
| U.S. Cl. 438—192 [438/137; 438/138; 438/173; 257/60; 257/135; 257/263; 257/E21.676] | 15 Claims |
| 1. A method for manufacturing a memory on a substrate having a plurality of shallow trench isolations formed therein, wherein
top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations
together define a vertical fin structure, the method comprising:
shrinking a width of the vertical fin structure of the substrate;
forming a cap layer on a top surface of the vertical fin structure of the substrate;
forming a carrier trapping layer over the substrate;
forming a conductive layer on the carrier trapping layer;
patterning the conductive layer and the carrier trapping layer to form a straddle gate structure, wherein the straddle structure
straddles over the vertical fin structure of the substrate; and
forming a first source/drain region and a second source/drain region in a portion of the vertical fin structure of the substrate
exposed by the straddle gate structure, wherein the straddle gate structure possesses a first carrier storage region and a
second carrier storage region located on opposite sidewalls of the vertical fin structure of the substrate between the first
source/drain region and the second source/drain region.
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