| US 7,350,027 B2 | ||
| Architectural support for thread level speculative execution | ||
| Alan G. Gara, Mount Kisco, N.Y. (US); and Valentina Salapura, Chappaqua, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Feb. 10, 2006, as Appl. No. 11/351,829. | ||
| Prior Publication US 2007/0192540 A1, Aug. 16, 2007 | ||
| Int. Cl. G06F 12/02 (2006.01) | ||
| U.S. Cl. 711—121 | 35 Claims |
| 1. An apparatus for supporting thread level speculative execution in a computing environment having multiple processing units
adapted for concurrent execution of threads in speculative and non-speculative modes, each processing unit having first and
second level caches operatively connected therewith for enabling multiprocessing, the apparatus comprising:
an additional cache level local at each said processing unit for use only in a thread level speculation mode, each said additional
cache for storing speculative results and status associated with its associated processor when handling speculative threads;
means for interconnecting each said additional cache level for forwarding speculative values and control data between parallel
executing threads; and
means for bypassing said additional cache level when no speculation processing thread is enabled at an associated processing
unit.
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