| US 7,349,250 B2 | ||
| Semiconductor device | ||
| Fumitoshi Ito, Hamura (Japan); Yoshiyuki Kawashima, Hitachinaka (Japan); Takeshi Sakai, Hitachinaka (Japan); Yasushi Ishii, Mito (Japan); Yasuhiro Kanamaru, Hitachinaka (Japan); Takashi Hashimoto, Iruma (Japan); Makoto Mizuno, Tokyo (Japan); Kousuke Okuyama, Kawagoe (Japan); and Yukiko Manabe, Yokohama (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Jul. 15, 2005, as Appl. No. 11/181,721. | ||
| Claims priority of application No. 2004-284123 (JP), filed on Sep. 29, 2004. | ||
| Prior Publication US 2006/0077713 A1, Apr. 13, 2006 | ||
| Int. Cl. G11C 11/34 (2006.01) | ||
| U.S. Cl. 365—185.05 [257/326] | 19 Claims |
| 1. A semiconductor device having multiple nonvolatile memory elements in which first gate electrodes are provided on a main
surface of a semiconductor substrate via a charge-storage film,
a first nonvolatile memory cell comprising one nonvolatile memory element of the multiple nonvolatile memory elements, and
a second nonvolatile memory cell comprising at least two nonvolatile memory elements of the multiple nonvolatile memory elements,
wherein a rewriting frequency of the second nonvolatile memory cell is greater than a rewriting frequency of the first nonvolatile
memory cell,
wherein, in the first nonvolatile memory cell, one bit is formed from the one nonvolatile memory element, and
wherein, in the second nonvolatile memory cell, one bit is formed from the at least two nonvolatile memory elements.
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