| US 7,348,653 B2 | ||
| Resistive memory cell, method for forming the same and resistive memory array using the same | ||
| Byeong-Ok Cho, Seoul (Korea, Republic of); Moon-Sook Lee, Seoul (Korea, Republic of); and Takahiro Yasue, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Apr. 13, 2006, as Appl. No. 11/279,640. | ||
| Claims priority of application No. 10-2005-0032470 (KR), filed on Apr. 19, 2005. | ||
| Prior Publication US 2007/0029546 A1, Feb. 08, 2007 | ||
| Int. Cl. H01L 27/01 (2006.01) | ||
| U.S. Cl. 257—516 [365/100; 365/148; 257/537; 257/E27.006; 257/E27.016; 257/E27.025; 257/E27.035; 257/E27.047; 257/E27.071; 257/E27.101; 257/E21.007; 257/E21.294; 257/E21.496; 438/238; 438/384; 438/FOR.189; 438/FOR.212] | 30 Claims |
| 1. A resistive memory cell comprising:
a substrate;
an insulating layer including a first electrode;
a photoimageable switchable memory element pattern including a first and a second surface, formed by exposing and developing
a photoimageable switchable material layer, and contacting the first electrode with the first surface; and
a second electrode contacting the photoimageable switchable memory element pattern with the second surface.
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