| US 7,509,598 B1 | ||
| Clock boosting systems and methods | ||
| Yinan Shen, Sunnyvale, Calif. (US); and Song Xu, Fremont, Calif. (US) | ||
| Assigned to Lattice Semiconductor Corporation, Hillsboro, Oreg. (US) | ||
| Filed on Apr. 19, 2007, as Appl. No. 11/737,702. | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—2 [716/22; 716/6; 716/18] | 16 Claims |
| 1. A method of configuring a programmable logic device comprising:
receiving routed data;
performing a software clock boost operation on the routed data to determine and include one or more desired clock delays for
circuit elements, wherein the software clock boost operation comprises:
performing a static timing analysis on the routed data;
determining a list of the desired clock delays; and
modifying the routed data to insert one or more routing wires to provide the desired clock delays; wherein the modifying comprises
cutting a switch on a routed connection of the routed data.
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