US 7,509,549 B2
Dynamic frequency scaling for JTAG communication
Lee Larson, Katy, Tex. (US); and Gilbert Laurenti, Saint Paul (France)
Assigned to Texas Instruments Incorporated, Dallas, Tex. (US)
Filed on Dec. 27, 2006, as Appl. No. 11/616,673.
Prior Publication US 2008/0163017 A1, Jul. 03, 2008
Int. Cl. G01R 31/28 (2006.01)
U.S. Cl. 714—726  [714/724] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a system under test (SUT) comprising a control logic; and
testing logic coupled to said SUT and adapted to provide to the SUT a clock signal to facilitate communications between the testing logic and the SUT;
wherein said control logic monitors a number of activated processors in a scan chain coupled to the control logic;
wherein, if said number of activated processors is reduced, the control logic dynamically decreases a frequency of said clock signal.