| US 7,509,547 B1 | ||
| System and method for testing of interconnects in a programmable logic device | ||
| Ui Sun Han, Santa Clara, Calif. (US); and Walter N. Sze, Lake Oswego, Oreg. (US) | ||
| Assigned to Xilinx, Inc., San Jose, Calif. (US) | ||
| Filed on Sep. 07, 2005, as Appl. No. 11/220,924. | ||
| Int. Cl. G01R 31/28 (2006.01); G01R 27/28 (2006.01); G01R 31/00 (2006.01); G01R 31/14 (2006.01); G11C 29/00 (2006.01); G06F 17/50 (2006.01); G06F 9/45 (2006.01); G06F 9/455 (2006.01); H03K 17/693 (2006.01); H03K 19/00 (2006.01) | ||
| U.S. Cl. 714—725 [714/724; 714/742; 714/719; 714/736; 714/737; 714/733; 714/734; 716/17; 716/16; 716/18; 716/8; 716/10; 716/12; 702/117; 702/118; 702/119; 702/120] | 19 Claims |
| 1. A processor-implemented method for testing interconnects of a programmable logic device (PLD), comprising:
reading data descriptive of a subset of interconnects of the PLD from a database;
wherein the PLD includes a plurality of different types of interconnection elements, and each interconnection element includes
a plurality of interconnects;
selecting a representative one of each type of interconnection element in the PLD, wherein the subset of interconnects includes
at least one of the plurality of interconnects from each representative one interconnection element;
wherein testing of the interconnects is limited to the representative ones of the different types of interconnection elements;
for each of the interconnects in the subset of interconnects, generating a respective test design that replaces a portion
of a coupling between an input pad and an output pad in an archetypal test design with a coupling that includes the interconnect;
generating from each of the test designs a respective configuration for the PLD;
simulating for each of the configurations a respective operation of the PLD programmed with the configuration; and
for each of the operations of the PLD, checking the operation of the PLD for inconsistency with an expected result.
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