| US 7,509,391 B1 | ||
| Unified memory management system for multi processor heterogeneous architecture | ||
| Gerard Chauvel, Antibes (France); Serge Lasserre, Frejus (France); and Dominique Benoit Jacques d'Inverno, Villeneuve Loubet (France) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on Nov. 23, 1999, as Appl. No. 9/448,569. | ||
| Int. Cl. G06F 15/167 (2006.01) | ||
| U.S. Cl. 709—214 [709/213; 709/215; 709/216; 711/154; 711/206; 711/207] | 17 Claims |
| 1. A multi-processor processing system comprising:
a shared memory for being accessed by multiple devices;
a plurality of processing devices external to said shared memory having respective dedicated memory management units for translating
virtual memory addresses, used internally by the processing devices to access locations in said shared memory, to physical
memory addresses corresponding to shared memory locations, where the dedicated memory management units each translate according
to tables maintained separately from other of the dedicated memory management units; and
a global unified memory management system for allocating the shared memory to a plurality of tasks executed on the processing
devices, to allocate one or more of the tasks with areas of said shared memory separate from address spaces of shared memory
allocated to other tasks.
|