| US 7,509,366 B2 | ||
| Multiplier array processing system with enhanced utilization at lower precision | ||
| Craig C. Hansen, Los Altos, Calif. (US) | ||
| Assigned to Microunity Systems Engineering, Inc., Sunnyvale, Calif. (US) | ||
| Filed on Apr. 18, 2003, as Appl. No. 10/418,113. | ||
| Application 10/418113 is a continuation of application No. 09/377182, filed on Aug. 19, 1999, granted, now 6,584,482. | ||
| Application 09/377182 is a continuation of application No. 08/857596, filed on May 16, 1997, granted, now 5,953,241. | ||
| Application 08/857596 is a continuation in part of application No. 08/516036, filed on Aug. 16, 1995, granted, now 5,742,840. | ||
| Claims priority of provisional application 60/021132, filed on May 17, 1996. | ||
| Prior Publication US 2004/0015533 A1, Jan. 22, 2004 | ||
| Int. Cl. G06F 7/50 (2006.01); G06F 7/52 (2006.01) | ||
| U.S. Cl. 708—501 | 19 Claims |
| 1. A method for performing a group-multiply-add instruction in a programmable processor, the method comprising:
partitioning a first register, a second register, and a third register into a plurality of floating-point operands;
multiplying, in parallel, the plurality of floating-point operands from the first register by the plurality of floating-point
operands from the second register and adding the plurality of floating-point operands from the third register, producing a
plurality of floating-point numbers; and
providing the plurality of floating-point numbers to a plurality of partitioned fields of a result.
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