| US 7,508,728 B2 | ||
| Methods and apparatus to provide refresh for global out of range read requests | ||
| Steve Richard Jahnke, Tokyo (Japan); and Hiromichi Hamakawa, Ibaraki (Japan) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on Aug. 30, 2006, as Appl. No. 11/512,675. | ||
| Prior Publication US 2008/0056043 A1, Mar. 06, 2008 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—222 [365/230.06] | 22 Claims |
| 1. A column address decoder to address one of a plurality of memory blocks in a memory array, each of the memory blocks having
up to a four bit address, the column address decoder comprising:
a column address input including two least significant bit column address lines, a third least significant bit column address
line, and a most significant bit column address line;
a plurality of block driver logic devices, each coupled to one of the plurality of memory blocks, the block driver logic devices
to produce a select signal to refresh the memory block;
a first logic decoder coupled to the two least significant column address lines, the first logic decoder producing four outputs
each corresponding to one of the four values of the two least significant column address lines;
a second logic decoder coupled to the third least significant and the most significant bit column address lines, the second
logic decoder producing four outputs each corresponding to one of the four values of the third least significant and the most
significant bit column address lines; and
wherein the outputs of the first and second logic decoders are connectable to the plurality of block driver logic devices
to produce the select signal from one of the plurality of block driver logic devices based on an up to four bit address received
on the column address input.
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