	US 7,508,714 B2
	Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block
Luca G. Fasoli, San Jose, Calif. (US); Roy E. Scheuerlein, Cupertino, Calif. (US); En-Hsing Chen, Sunnyvale, Calif. (US); Sucheta Nallamothu, San Jose, Calif. (US); Maitreyee Mahajani, Saratoga, Calif. (US); and Andrew J. Walker, Mountain View, Calif. (US)
Assigned to SanDisk 3D LLC, Milpitas, Calif. (US)
Filed on May 21, 2007, as Appl. No. 11/751,567.
Application 11/751567 is a continuation of application No. 10/729843, filed on Dec. 05, 2003, granted, now 7,221,588.
Prior Publication US 2007/0217263 A1, Sep. 20, 2007
Int. Cl. G11C 11/34 (2006.01); G11C 16/04 (2006.01)

U.S. Cl. 365—185.18 [365/185.05; 365/185.06]

17 Claims

1. An integrated circuit comprising:

a memory array having at least two planes of memory cells formed above a substrate, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof;

wherein each respective NAND string within a given memory block of a given memory plane is coupled to a respective global bit line that is not shared by other NAND strings within the given memory block of the given memory plane, and wherein some adjacent NAND strings within a memory block are coupled at opposite ends thereof to their respective global bit lines;

wherein half of said NAND strings within the given memory block are each coupled at one end thereof to its respective global bit line, and the other half of said NAND strings within the given memory block are each coupled at the other end thereof to its respective global bit line;

wherein each NAND string of a first group of M adjacent NAND strings within the given memory block is coupled at one end thereof to its respective global bit line, and each NAND string of an adjacent second group of M adjacent NAND strings within the given memory block is coupled at the other end thereof to its respective global bit line; and

wherein a respective NAND string within the first group of M adjacent NAND strings is adjacent to a respective NAND string within the second group of M adjacent NAND strings, and are coupled at opposite ends thereof to their respective global bit lines.