| US 7,508,707 B2 | ||
| Semiconductor storage apparatus | ||
| Kiyoshi Nakai, Tokyo (Japan); Kazuhiko Kajigaya, Tokyo (Japan); and Isamu Asano, Tokyo (Japan) | ||
| Assigned to Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Dec. 31, 2007, as Appl. No. 12/3,734. | ||
| Application 12/003734 is a division of application No. 11/409088, filed on Apr. 24, 2006, granted, now 7,333,363. | ||
| Claims priority of application No. 2005-126457 (JP), filed on Apr. 25, 2005. | ||
| Prior Publication US 2008/0130390 A1, Jun. 05, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 14/00 (2006.01) | ||
| U.S. Cl. 365—185.08 [365/151] | 6 Claims |
| 1. A semiconductor device comprising:
a first memory array consisting of a plurality of volatile memory cells storing data;
a second memory array consisting of a plurality of non-volatile memory cells storing data;
a sense amplifier provided between said first and second memory arrays, and shared between said first and second memory arrays;
a first switch for on/off controlling a connection between a bit line of said first memory array and said sense amplifier;
and
a second switch for on/off controlling a connection between a bit line of said second memory array and said sense amplifier;
wherein a data transfer from each of said first memory array and said second memory array to the other memory array is carried
out through said sense amplifier.
|