| US 7,508,054 B2 | ||
| Semiconductor device and a method of manufacturing the same | ||
| Fujiaki Nose, Ome (Japan); Hiroshi Kikuchi, Hidaka (Japan); Satoshi Ueno, Ome (Japan); and Norio Nakazato, Kashiwa (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan) | ||
| Filed on Jun. 16, 2005, as Appl. No. 11/153,359. | ||
| Application 11/153359 is a continuation of application No. 10/621411, filed on Jul. 18, 2003, granted, now 6,924,549. | ||
| Claims priority of application No. 2002-250506 (JP), filed on Aug. 29, 2002. | ||
| Prior Publication US 2005/0233501 A1, Oct. 20, 2005 | ||
| Int. Cl. H01L 23/495 (2006.01) | ||
| U.S. Cl. 257—667 [257/E23.047; 257/666; 257/668; 257/675; 438/111; 438/112; 438/123; 29/827] | 6 Claims |

| 1. A method of manufacturing a semiconductor device assembled by using a lead frame, comprising the steps of:
(a) providing a lead frame, the lead frame having a die pad smaller than a main surface of a semiconductor chip and a plurality
of leads each comprising an outer terminal portion and an inner lead portion, the inner lead portions of the leads being bent
in a direction away from a surface on which the outer lead portions of the leads are arranged;
(b) providing the semiconductor chip, the semiconductor chip having a semiconductor element and a plurality of electrodes;
(c) protruding the semiconductor chip from the die pad and bonding a back side of the semiconductor chip and the die pad with
each other;
(d) connecting the electrodes of the semiconductor chip and corresponding said inner lead portions of the lead frame electrically
with each other through bonding wires;
(e) sealing the semiconductor chip, the bonding wires and the plural inner lead portions with resin to form a sealing member
in such a manner that the outer terminal portions of the leads are exposed to a mounting surface of the sealing member and
that the inner lead portions of the leads are disposed inside the sealing member; and
separating the plural leads from the lead frame,
wherein the semiconductor chip provided in the step (b) comprises:
a first wiring formed on a semiconductor substrate and connected electrically to a ground potential;
a first insulating film formed on the first wiring; and
a second wiring formed on the first insulating film and serving as a signal transmission line,
the second wiring including a first region, a second region, and a third region,
the second region of the second wiring being positioned between the first region and the third region,
with bonding wires being connected to the first region of the second wiring, and
the width of the second wiring in the second region being larger than the width thereof in the third region.
|