	US 7,507,612 B2
	Flat panel display and fabrication method thereof
Han-Chung Lai, Taoyuan (Taiwan); and Ta-Wen Liao, Miaoli (Taiwan)
Assigned to AU Optronics Corp., Hsinchu (Taiwan)
Filed on Dec. 14, 2006, as Appl. No. 11/610,528.
Application 11/610528 is a division of application No. 10/819382, filed on Apr. 06, 2004, granted, now 7,170,092.
Claims priority of application No. 92112780 A (TW), filed on May 12, 2003.
Prior Publication US 2007/0082435 A1, Apr. 12, 2007
Int. Cl. H01L 21/00 (2006.01)

U.S. Cl. 438—149 [438/151; 257/E29.151; 345/92]

10 Claims

1. A method for forming a flat panel display, comprising:

providing a substrate;

forming a first conducting layer on the substrate, the first conducting layer comprising a gate electrode;

covering a first insulating layer on the first conducting layer and the substrate;

covering a semiconductor layer on the first insulating layer;

covering a doped semiconductor layer on the semiconductor layer;

covering a second conducting layer on the doped semiconductor layer;

forming a first resist layer on the second conducting layer;

performing a first wet etching on the second conducting layer such that the doped semiconductor layer is exposed and the first resist layer overhangs an edge of the second conducting layer, wherein a gap between the edge of the second conducting layer and edge of the first resist layer is a first distance;

performing a first dry etching on the doped semiconductor layer and the semiconductor layer, wherein the first resist layer undergoes partial ashing to a second resist layer;

performing a second wet etching on the second conducting layer such that the second resist layer overhangs the edge of the second conducting layer, wherein a gap between the edge of the second conducting layer and an edge of the doped semiconductor layer is a second distance, and a source electrode and a drain electrode are defined within the second conducting layer; and

performing a second dry etching on the doped semiconductor layer to form a source and a drain within the doped semiconductor layer.