forming a gate line, a gate electrode, and a gate pad electrode on a substrate;

sequentially forming a gate insulating layer, a semiconductor layer and a metal layer on an entire surface of the substrate including the gate electrode;

forming a first photoresist on the metal layer;

patterning the semiconductor layer, a data line, source and drain electrodes, and a data pad electrode by selectively etching the gate insulating layer, the semiconductor layer, and the metal layer using the first photoresist as a mask;

forming a second photoresist to cover the gate pad electrode;

forming a passivation layer on an entire surface of the substrate including the first and second photoresists;

removing the passivation layer on the first and second photoresists by lift-stripping the first and second photoresists; and

forming a pixel electrode electrically connected to the drain electrode,

wherein the patterning the semiconductor layer, the data line, the source and drain electrodes, and the data pad electrode by selectively etching the gate insulating layer, the semiconductor layer, and the metal layer using the first photoresist as a mask includes;

forming the semiconductor layer, the data line, and the data pad electrode by etching together the gate insulating layer, the semiconductor layer, and the metal layer using the first photoresist as a mask;

ashing the first photoresist; and

forming the source and drain electrodes by patterning the metal layer above the semiconductor layer using the ashed first photoresist as a mask.