US 7,346,886 B2
Method and apparatus for determining chip arrangement position on substrate
Youzou Fukagawa, Tochigi-ken (Japan); and Mario Nakamori, Yokohama (Japan)
Assigned to Canon Kabushiki Kaisha, Tokyo (Japan)
Filed on Apr. 12, 2005, as Appl. No. 11/103,459.
Claims priority of application No. 2004-118223 (JP), filed on Apr. 13, 2004.
Prior Publication US 2005/0253215 A1, Nov. 17, 2005
Int. Cl. G06F 17/50 (2006.01)
U.S. Cl. 716—21  [716/19] 5 Claims
OG exemplary drawing
 
1. A method of determining a relative position between a chip lattice comprised of rectangular cells, each of which has a size of a chip to be formed on a substrate and an effective area on the substrate, said method comprising:
a division step of dividing one representative cell in the chip lattice into a plurality of partial areas in accordance with an existing area, of a representative point of the effective area, in which chip sets trimmed from the chip lattice with the effective area are identical;
a specifying step of specifying a partial area corresponding to a chip set including a maximum number of chips from the plurality of partial areas; and
a setting step of setting the representative point in the partial area specified in said specifying step,
wherein said division step obtains, as a boundary of the partial area, a locus of the representative point in the representative cell by moving the effective area so that a cell which has a lattice point selected from the chip lattice as a lattice point farthest from the representative point is included in the effective area and a periphery of the effective area is in contact with the selected lattice point,
wherein the lattice point selected in said division step is within a locus of the periphery of the effective area corresponding to the movement of the representative point in the representative cell,
wherein an effective arc is obtained by excluding from the periphery an arc which has, at two ends thereof, intersections, between a line parallel to a vertical line of the chip lattice and the periphery of the effective area, having a distance equal to a vertical dimension of the cell, and an arc which has, at two ends thereof, intersections, between a line parallel to a horizontal line of the chip lattice and the periphery of the effective area, having a distance equal to a horizontal dimension of the cell, and a closed curve is obtained with the effective arc and a line segment which connects the two ends of the excluded arc, and
the lattice point selected in said division step is within a locus of the closed curve corresponding to the movement of the representative point in the representative cell.