| US 7,506,080 B2 | ||
| Parallel processing of frame based data transfers | ||
| Victor Lau, Marlborough, Mass. (US); Pak-lung Seto, Shrewsbury, Mass. (US); Suresh Chemudupati, Marlborough, Mass. (US); Naichih Chang, Shrewsbury, Mass. (US); and William Halleck, Lancaster, Mass. (US) | ||
| Assigned to Inter Corporation, Santa Clara, Calif. (US) | ||
| Filed on Sep. 16, 2005, as Appl. No. 11/229,100. | ||
| Prior Publication US 2007/0067504 A1, Mar. 22, 2007 | ||
| Int. Cl. G06F 13/28 (2006.01); G06F 13/00 (2006.01); H04L 12/28 (2006.01); H04L 12/56 (2006.01) | ||
| U.S. Cl. 710—22 [710/33; 710/110; 370/395.5; 370/412] | 16 Claims |
| 1. A frame based data transfer device comprising:
a receive frame parser to receive a frame, to store framing information from the frame in a receive header queue, and to store
an information unit from the frame in an information unit buffer;
a receive frame processor coupled to the receive header queue, the receive frame processor to perform transport layer tasks
including reading a transport layer task context as determined by a tag field in the framing information, to determine how
to handle the frame from the transport layer task context and the framing information, generating a DMA descriptor, and storing
an updated transport layer task context; and
a direct memory access (DMA) engine coupled to the information unit buffer and the receive frame processor, the DMA engine
to perform DMA tasks including reading a DMA task context, transferring the information unit to a destination memory by processing
the DMA descriptor, and storing an updated DMA task context, wherein the DMA engine performs the DMA tasks and the receive
frame processor performs the transport layer tasks concurrently with one another.
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