| US 7,505,357 B2 | ||
| Column/row redundancy architecture using latches programmed from a look up table | ||
| Vinod Lakhani, Palo Alto, Calif. (US); and Benjamin Louie, Fremont, Calif. (US) | ||
| Assigned to Micron Technology Inc., Boise, Id. (US) | ||
| Filed on Oct. 11, 2006, as Appl. No. 11/508,325. | ||
| Application 11/508325 is a continuation of application No. 10/206044, filed on Jul. 29, 2002, granted, now 7,120,068. | ||
| Prior Publication US 2007/0038906 A1, Feb. 15, 2007 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—230.08 [365/200; 365/233.5; 365/225.7] | 20 Claims |
| 1. A memory device, comprising:
a remapping circuit for remapping defective memory locations, said remapping circuit comprising:
a group of sets of reloadable latches,
said remapping circuit being configured, upon a change in an incoming address, to reload said group of sets of reloadable
latches with stored redundancy information associated with the incoming address, wherein each set of reloadable latches comprises:
a first subset of reloadable latches for loading a defective memory address; and
a second subset of reloadable latches for loading a replacement memory address.
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