| US 7,505,356 B2 | ||
| Multi-column addressing mode memory system including an integrated circuit memory device | ||
| Frederick A. Ware, Los Altos Hills, Calif. (US); Lawrence Lai, San Jose, Calif. (US); Chad A. Bellows, Burlingame, Calif. (US); and Wayne S. Richardson, Saratoga, Calif. (US) | ||
| Assigned to Rambus Inc., Los Altos, Calif. (US) | ||
| Filed on Sep. 11, 2007, as Appl. No. 11/853,708. | ||
| Application 11/853708 is a continuation of application No. 10/955193, filed on Sep. 30, 2004, granted, now 7,280,428. | ||
| Prior Publication US 2008/0062807 A1, Mar. 13, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 8/14 (2006.01) | ||
| U.S. Cl. 365—230.06 [365/189.04; 365/230.03; 365/233; 711/5; 711/168] | 28 Claims |
| 1. An integrated circuit memory device comprising:
a storage array;
a row decoder to retrieve a row of data from a row of storage cells within the storage array; and
column decoder circuitry to enable read and write access to address-specified columns of data within the row of data retrieved
by the row decoder, the column decoder circuitry including circuitry to decode a single column address per column cycle interval
in a first mode of operation and to decode at least two column addresses per column cycle interval in a second mode of operation.
|