| US 7,505,348 B2 | ||
| Balanced and bi-directional bit line paths for memory arrays with programmable memory cells | ||
| John K. De Brosse, Colchester, Vt. (US); and Mark C. H. Lamorey, South Burlington, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Oct. 06, 2006, as Appl. No. 11/539,233. | ||
| Prior Publication US 2008/0084734 A1, Apr. 10, 2008 | ||
| Int. Cl. G11C 7/02 (2006.01) | ||
| U.S. Cl. 365—214 [365/163; 365/190; 365/230.06] | 16 Claims |
| 1. A memory system comprising:
a plurality of memory cells;
a plurality of bit lines, wherein each of said memory cells is coupled to two of said bit lines; and
a plurality of isolation devices coupled to said bit lines and configured to establish current pathways through said bit lines
and said memory cells such that a resistance of each of said current pathways is approximately equal for all memory cell locations
within said system, and
wherein said memory cells each comprise:
an access transistor comprising:
a first source/drain region coupled to one of said two of said bit lines; and
a second source/drain region; and
a programmable resistor comprising:
a first terminal coupled to said second source/drain region; and
a second terminal coupled to another of said two of said bit lines.
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