| US 7,505,334 B1 | ||
| Measurement method for reading multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition | ||
| Matthew J. Breitwisch, Yorktown Heights, N.Y. (US); Chung H. Lam, Peekskill, N.Y. (US); and Bipin Rajendran, White Plains, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on May 28, 2008, as Appl. No. 12/128,291. | ||
| Int. Cl. G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 16/26 (2006.01); G11C 11/4197 (2006.01); G11C 11/4193 (2006.01); G11C 16/06 (2006.01) | ||
| U.S. Cl. 365—189.15 [365/163; 365/158; 365/148; 365/185.21; 365/202; 365/201; 365/189.07] | 1 Claim |
| 1. A method for operating a memory cell in which a variation of the characteristic parameter of the memory cell affects the
effective resistance of the memory cell, the method comprising:
measuring a first discharge time of a reference voltage through the memory cell;
determining that the first discharge time is less than a minimum discharge time;
adding a supplemental capacitor in parallel with the memory cell, adding including coupling the capacitor to the memory cell
through a switch;
measuring a second discharge time of the reference voltage through the memory cell;
storing the second discharge time; and
determining the value stored in the memory cell based on the second discharge time;
wherein measuring the first and second discharge times includes pre-charging an electronic circuit coupled to the memory cell,
activating the memory cell so as to discharge the electronic circuit, at least partially through the memory cell, starting
a time measurement when the memory cell is activated, and stopping the time measurement when the voltage level in the electronic
circuit falls below a pre-defined reference voltage.
|