	US 7,503,021 B2
	Integrated circuit diagnosing method, system, and program product
Matt Boucher, Colchester, Vt. (US); John M. Cohn, Richmond, Vt. (US); Richard Dauphin, Shelburne, Vt. (US); Mark Masters, Essex Junction, Vt. (US); Judith H. McCullen, Essex Junction, Vt. (US); Sarah C. Braasch, Richmond, Vt. (US); and Michael H. Sitko, Jericho, Vt. (US)
Assigned to International Business Machines Corporation, Armonk, N.Y. (US)
Filed on Jun. 16, 2005, as Appl. No. 11/160,266.
Application 11/160266 is a continuation of application No. PCT/US02/40429, filed on Dec. 17, 2002.
Prior Publication US 2005/0278667 A1, Dec. 15, 2005
Int. Cl. G06F 17/50 (2006.01)

U.S. Cl. 716—4 [716/5]

17 Claims

1. A method of diagnosing an integrated circuit including at least one circuit layer, the method comprising the steps of:

capturing at least one image for each of the at least one circuit layer;

converting the at least one image into a layout;

defining port information and power information in the layout;

extracting component information from the layout;

extracting net connectivity from the layout;

generating a component netlist wherein the component netlist is based on the extracted component information and net connectivity information; and

generating a logic netlist based on the component netlist by applying hierarchical composition rules to replace at least one circuit element in the component netlist with an equivalent logical component.