| US 7,503,020 B2 | ||
| IC layout optimization to improve yield | ||
| Robert J. Allen, Jericho, Vt. (US); Faye D. Baker, Burlington, Vt. (US); Albert M. Chu, Essex, Vt. (US); Michael S. Gray, Fairfax, Vt. (US); Jason Hibbeler, Williston, Vt. (US); Daniel N. Maynard, Craftsbury Common, Vt. (US); Mervyn Y. Tan, Milton, Vt. (US); and Robert F. Walker, St. George, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jun. 19, 2006, as Appl. No. 11/424,922. | ||
| Prior Publication US 2007/0294648 A1, Dec. 20, 2007 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—2 [716/5] | 15 Claims |
| 1. A method of improving yield comprising:
identifying a critical area region of a design having at least one structure by comparing a plurality of manufacturability
data to the design;
defining a plurality of constraints, which bound the degree to which a change is made to the design, by
providing a plurality of design rules;
providing a plurality of design functionality requirements;
identifying and storing a plurality of critical area data; and
developing a plurality of objectives that satisfies the given rules and requirements using the critical area data;
the plurality of objectives are selected from at least one of the group consisting of piece-wise linear, pair-wise, spacing,
common run, critical area, and distance; and
performing the change to the design, according to at least one of the plurality of objectives and bounded within the plurality
of constraints, such that the critical area region of the design is reduced.
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