| US 7,502,979 B2 | ||
| Pipelined scan structures for testing embedded cores | ||
| Jayabrata Ghosh Dastidar, San Jose, Calif. (US) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Jun. 10, 2005, as Appl. No. 11/150,354. | ||
| Prior Publication US 2006/0282729 A1, Dec. 14, 2006 | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—729 | 28 Claims |
| 20. An integrated circuit having logic for scan testing, comprising:
a logic under test;
a plurality of input-side scan chains operable to receive input test data in parallel and to make available the input test
data for applying to the logic under test, wherein at least two input-side scan chains are on different levels of a pipeline;
and
a plurality of output-side scan chains operable to receive output test data from the logic under test and to make available
the output test data for observation from the output-side scan chains in parallel, wherein at least two output-side scan chains
are on different levels of the pipeline.
|