| US 7,502,918 B1 | ||
| Method and system for data dependent performance increment and power reduction | ||
| Harry Barowski, Boeblingen (Germany); Tobias Gemmeke, Santa Clara, Calif. (US); Tim Niggemeier, Laatzen (Germany); and Thomas Pflueger, Leinfelden (Germany) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Mar. 28, 2008, as Appl. No. 12/58,256. | ||
| Int. Cl. G06F 9/30 (2006.01) | ||
| U.S. Cl. 712—226 [712/209] | 1 Claim |

| 1. A method of dispatching instructions, comprising:
dispatching original instructions into an instruction buffer, the original instructions including at least one operand;
renaming the at least one operand;
selecting the original instructions from the instruction buffer;
sending selected instructions with explicit bits, which comprise values stored in a mapper table for each of a plurality of
physical registers, to an internal operation code exchange table, which includes replacement rules for replacing the selected
instructions with a simplified instruction based on the original instructions and the explicit bits;
replacing the selected instructions with the simplified instruction in accordance with the explicit bits; and
issuing the simplified instructions indirectly to an execution unit by sending the simplified instruction and all explicit
bits for the operands to a content addressable memory address logic of the internal operation code exchange table, wherein
if a bitvector, consisting of the original instruction and the explicit bits, matches a pattern stored in the internal operation
code exchange table, the original instruction is replaced by the simplified instruction.
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