| US 7,502,913 B2 | ||
| Switch prefetch in a multicore computer chip | ||
| Paul R. Barham, Cambridge (United Kingdom) | ||
| Assigned to Microsoft Corporation, Redmond, Wash. (US) | ||
| Filed on Jun. 16, 2006, as Appl. No. 11/454,245. | ||
| Prior Publication US 2007/0294516 A1, Dec. 20, 2007 | ||
| Int. Cl. G06F 9/30 (2006.01) | ||
| U.S. Cl. 712—214 | 15 Claims |
| 1. A method for fetching data for a processor of a plurality of processors on a multi-processor computer chip, comprising:
receiving, by a first processor of said plurality of processors, a list comprising at least one data address and a corresponding
code address, wherein the at least one data address of the list may be executed in any order without affecting a result of
a program corresponding to the at least one data address;
receiving, by said first processor, a processor instruction to execute the data address in the list available in a shortest
interval;
determining, by said first processor, the data address in the list that the processor may begin executing in a shortest interval;
and
executing, by said first processor, at least one instruction corresponding to the code address corresponding to the at least
one data address that is available in the shortest interval.
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