| US 7,502,912 B2 | ||
| Method and apparatus for rescheduling operations in a processor | ||
| Avinash Sodani, Hillsboro, Oreg. (US); Per H. Hammarlund, Hillsboro, Oreg. (US); and Stephan J. Jourdan, Portland, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Dec. 30, 2003, as Appl. No. 10/749,272. | ||
| Prior Publication US 2005/0149689 A1, Jul. 07, 2005 | ||
| Int. Cl. G06F 9/38 (2006.01) | ||
| U.S. Cl. 712—214 | 24 Claims |
| 9. A computer processing system comprising:
a memory device to store instructions;
a processor coupled to said memory device and to execute said instructions, said processor including:
a re-scheduler having a first input coupled to an instruction queue, a second input coupled to a replay unit, and an output;
a scheduler coupled to said re-scheduler output;
a replay system having a first and second outputs, said first output coupled to an execution unit and second output coupled
to said re-scheduler;
wherein said re-scheduler comprises:
a re-scheduler device coupled to an instruction queue to receive an instruction, before the instruction being first sent to
the scheduler;
a delay unit coupled to said re-scheduler device to store wait history for said instruction; and
a delay queue coupled to the output of said re-scheduler device to hold said instruction for a fixed number of clock cycles,
the fixed number of cycles independent of the current availability of input data to the instruction.
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