| US 7,502,910 B2 | ||
| Sideband scout thread processor for reducing latency associated with a main processor | ||
| Peter C. Damron, Fremont, Calif. (US) | ||
| Assigned to Sun Microsystems, Inc., Santa Clara, Calif. (US) | ||
| Filed on Jan. 28, 2003, as Appl. No. 10/352,495. | ||
| Prior Publication US 2004/0148491 A1, Jul. 29, 2004 | ||
| Int. Cl. G06F 15/00 (2006.01); G06F 15/76 (2006.01) | ||
| U.S. Cl. 712—34 [712/207; 712/235] | 56 Claims |
| 1. A method for executing a main thread, comprising:
obtaining the main thread, wherein the main thread comprises a plurality of instructions;
obtaining sideband information associated with the main thread;
selecting a first instruction of the plurality of instructions using the sideband information, wherein the first instruction
retrieves a value;
executing the first instruction using a first processor to load the value from a main memory to a cache memory; and
executing the first instruction using a second processor to retrieve the value from the cache memory after executing the first
instruction using the first processor.
|