a phase locked loop circuit comprising a first modulation input at a node having a high-pass filter response associated therewith, and comprising a second modulation input at a node having a low-pass filter response associated therewith, wherein the phase locked loop circuit receives a reference frequency signal as an input and outputs a modulated radio frequency signal;

a frequency generation block configured to receive the reference frequency signal and output a substantially constant frequency digital clock signal;

a digital signal processor configured to receive the digital clock signal and generate digital modulation data;

a digital filter configured to receive the digital clock signal and the digital modulation data and provide digital conditioning of the digital modulation data, wherein the digital filter and the digital signal processor are synchronized with respect to one another based on the digital clock signal and operate independently of a frequency of the reference frequency signal;

a sigma-delta modulator coupled between the second node and the digital filter, wherein the sigma-delta modulator comprises a clock input that receives the reference frequency signal; and

a synchronization unit coupled between an output of the digital filter and an input of the sigma-delta modulator,

wherein the conditioned digital modulation data is employed at the second node for digital modulation via the sigma-delta modulator, and

wherein an analog modulation signal is derived from the digital modulation data and is employed at the first node for analog modulation.