| US 7,502,428 B2 | ||
| Pseudo-noise encoded digital data clock recovery | ||
| David Gordon Ballinger, San Francisco, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Nov. 15, 2005, as Appl. No. 11/280,721. | ||
| Application 11/280721 is a continuation of application No. 09/576056, filed on May 23, 2000, granted, now 6,980,586. | ||
| Claims priority of provisional application 60/135571, filed on May 24, 1999. | ||
| Prior Publication US 2006/0067386 A1, Mar. 30, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H04L 27/06 (2006.01); H04L 7/00 (2006.01) | ||
| U.S. Cl. 375—343 [375/355; 375/367] | 20 Claims |
| 1. An apparatus comprising:
a correlator to correlate a pseudo-noise sequence with a received chip stream to generate a correlated output;
a phase controller coupled to the correlator, the phase controller to generate a histogram of the correlated output over a
plurality of bit periods, wherein the phase controller includes a plurality of counters; and
a bit clock generator coupled to the phase controller, the bit clock generator to recover an original bit stream by using
the histogram to adjust a sample position of a bit clock, wherein the bit clock generator adjusts the sample position of the
bit clock to a position where a corresponding counter exceeds a threshold, and wherein the bit clock generator retains the
sample position of the bit clock where no counters exceed the threshold.
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