| US 7,502,380 B2 | ||
| Packet handler | ||
| Ken'ichi Sakamoto, Tokyo (Japan); Yasunari Shinohara, Kawasaki (Japan); and Takahiko Kozaki, Tokyo (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan) | ||
| Filed on Dec. 08, 2004, as Appl. No. 11/6,636. | ||
| Application 11/006636 is a continuation of application No. 09/955159, filed on Sep. 19, 2001, granted, now 6,850,485. | ||
| Application 09/955159 is a continuation of application No. 09/210849, filed on Dec. 15, 1998, granted, now 6,327,244. | ||
| Application 09/210849 is a continuation of application No. 08/826523, filed on Apr. 03, 1997, granted, now 5,903,544. | ||
| Claims priority of application No. 8-083550 (JP), filed on Apr. 05, 1996. | ||
| Prior Publication US 2005/0100044 A1, May 12, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H04L 12/28 (2006.01) | ||
| U.S. Cl. 370—419 [370/390; 370/395.1; 370/389] | 5 Claims |
| 1. A packet transmission apparatus comprising:
a plurality of line interfaces;
a switch for switching packets; and
a circuit for, upon receiving of packets by said plurality of line interfaces, determining whether to transfer the packets
to said switch or to block the packets so as not to transfer the packets to said switch,
wherein if the packets received by said plurality of line interfaces respectively are a pair of packets that are redundant
with respect to each other, then said circuit transfers one packet of the pair of redundant packets to said switch and blocks
the other packet of the pair of redundant packets, and
wherein if the packets received by said plurality of line interfaces respectively are not a pair of packets that are redundant
with respect to each other, then said circuit transfers the packets received by said plurality of line interfaces.
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