| US 7,502,275 B2 | ||
| Semiconductor memory device | ||
| Koji Nii, Tokyo (Japan); Shigeki Obayashi, Tokyo (Japan); Hiroshi Makino, Tokyo (Japan); Koichiro Ishibashi, Tokyo (Japan); and Hirofumi Shinohara, Tokyo (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on May 23, 2006, as Appl. No. 11/438,668. | ||
| Claims priority of application No. 2005-149265 (JP), filed on May 23, 2005; and application No. 2006-107643 (JP), filed on Apr. 10, 2006. | ||
| Prior Publication US 2006/0262628 A1, Nov. 23, 2006 | ||
| Int. Cl. G11C 5/14 (2006.01) | ||
| U.S. Cl. 365—226 [365/154; 365/189.07; 365/189.08; 365/196; 365/230.03; 365/189.09] | 10 Claims |
| 1. A semiconductor device comprising:
a plurality of memory cells arranged in rows and columns;
a plurality of bit lines, arranged corresponding to memory cell columns, each connected to the memory cells on a corresponding
column;
a plurality of cell power supply lines, arranged corresponding to the memory cell columns, each for supplying a first power
supply voltage to the memory cells on a corresponding column; and
a plurality of write assist circuits, arranged corresponding to the memory cell columns, each for selectively shutting off
supply of the first power supply voltage to a corresponding cell power supply line and to set the corresponding cell power
supply line to a floating state according at least to a voltage on the bit line in a corresponding column in a data write
operation.
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