| US 7,501,899 B2 | ||
| Method and device for generating a signal by fractional frequency locked loop | ||
| Sébastien Dedieu, Crolles (France); and Marc Houdebine, Grenoble (France) | ||
| Assigned to STMicroelectronics SA, Montrouge (France) | ||
| Filed on Dec. 20, 2005, as Appl. No. 11/312,127. | ||
| Claims priority of application No. 04 13596 (FR), filed on Dec. 20, 2004. | ||
| Prior Publication US 2006/0154616 A1, Jul. 13, 2006 | ||
| Int. Cl. H03L 7/00 (2006.01) | ||
| U.S. Cl. 331—16 [331/17; 331/34; 331/177 R; 327/156] | 24 Claims |
| 1. A method of generating a desired signal having a desired frequency equal to a product of a reference frequency of a reference
signal times a real number comprising an integer part and a decimal part, the method comprising:
cyclically performing a succession of a measurement phase and of a correction phase;
the measurement phase comprising
an integer division of a frequency of an output signal of an oscillator by a divider so as to obtain an intermediate signal,
a determination of measurement signals, responsive to a controller, representative of a time mismatch between the intermediate
signal and the reference signal having the reference frequency, and
a transfer of electric charge dependent on a reference period of the reference signal, and on the integer part and on the
decimal part of the real number so as to obtain an error signal representative of a time mismatch between a current output
signal period of the oscillator and a desired period based on the desired frequency of the desired signal;
the correction phase comprising a deactivation of the divider and a correction of the oscillator based on the error signal;
and
the output signal from the oscillator defining the desired signal.
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