| US 7,501,872 B2 | ||
| Clock-generator architecture for a programmable-logic-based system on a chip | ||
| Shin-Nan Sun, Fremont, Calif. (US); Limin Zhu, Fremont, Calif. (US); Theodore Speers, San Jose, Calif. (US); and Gregory Bakker, San Jose, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Oct. 12, 2007, as Appl. No. 11/871,741. | ||
| Application 11/871741 is a continuation of application No. 11/427717, filed on Jun. 29, 2006, granted, now 7,298,178. | ||
| Application 11/427717 is a continuation of application No. 10/903473, filed on Jul. 29, 2004, granted, now 7,102,391. | ||
| Application 10/903473 is a continuation in part of application No. 10/843701, filed on May 10, 2004, granted, now 7,170,315. | ||
| Claims priority of provisional application 60/491788, filed on Jul. 31, 2003. | ||
| Prior Publication US 2008/0030235 A1, Feb. 07, 2008 | ||
| Int. Cl. H03K 3/00 (2006.01) | ||
| U.S. Cl. 327—298 [327/99; 327/294] | 11 Claims |
| 1. A programmable system-on-a-chip integrated circuit device comprising:
an RC oscillator circuit;
a crystal oscillator circuit;
an external oscillator input;
a programmable logic block;
a clock conditioning circuit selectively coupleable to the RC oscillator circuit, the crystal oscillator circuit, the external
oscillator input, and the programmable logic block, the clock conditioning circuit comprising:
a first multiplexer having a first data input coupled to the RC oscillator circuit, a second data input coupled to the crystal
oscillator circuit, a third data input coupled to the external oscillator input, a set of select inputs coupled to the programmable
logic block, and an output;
a first programmable frequency divider circuit having an input coupled to the output of the first multiplexer, at least one
control input coupled to the programmable logic block, and an output;
a phase locked loop having an input coupled to the output of the first programmable divider circuit, a feedback input, and
an output;
a second programmable frequency divider circuit having an input coupled to the output of the phase locked loop, at least one
control input coupled to the programmable logic block, and an output coupled to the feedback input of the phase locked loop;
a second multiplexer having a first data input coupled to the RC oscillator circuit, a second data input coupled to the crystal
oscillator circuit, a third data input coupled to the external oscillator input, a fourth input coupled to the output of the
phase locked loop, a set of select inputs coupled to the programmable logic block, and an output;
a delay line having an input coupled to the output of the second multiplexer, at least one control input coupled to the programmable
logic block, and an output coupled to the programmable logic block; and
a real time clock having an input selectively coupleable to the RC oscillator circuit, the crystal oscillator circuit, and
the external oscillator input.
|