| US 7,501,863 B2 | ||
| Voltage margining with a low power, high speed, input offset cancelling equalizer | ||
| Bruce Querbach, Hillsboro, Oreg. (US); Randall B. Hamilton, Hillsboro, Oreg. (US); Luke A. Johnson, Queen Creek, Ariz. (US); and Minyoung Kim, Mather, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Mar. 14, 2007, as Appl. No. 11/724,128. | ||
| Prior Publication US 2008/0231356 A1, Sep. 25, 2008 | ||
| Int. Cl. H03K 17/00 (2006.01) | ||
| U.S. Cl. 327—94 [327/91] | 4 Claims |
| 1. A circuit comprising:
an amplifier comprising a first input port and a second input port;
a first capacitor connected to first input port of the amplifier;
a second capacitor connected to the second input port of the amplifier;
a voltage source comprising:
a current source;
a first set of pMOSFETs connected to the current source;
a second set of pMOSFETs connected to the current source;
a first node connected to the first set of pMOSFETs and coupled to the first capacitor when the first switch is closed; and
a second node connected to the second set of pMOSFETs and coupled to the second capacitor when the second switch is closed;
a first switch to couple the first capacitor to the voltage source when closed; and
a second switch to couple the second capacitor to the voltage source when closed.
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