| US 7,501,860 B2 | ||
| Differential input driver using current feedback and cross-coupled common base devices | ||
| Andrew Fitting, Sunnyvale, Calif. (US); and Michael Maida, San Jose, Calif. (US) | ||
| Assigned to National Semiconductor Corporation, Santa Clara, Calif. (US) | ||
| Filed on Dec. 03, 2007, as Appl. No. 11/949,333. | ||
| Claims priority of provisional application 60/953166, filed on Jul. 31, 2007. | ||
| Prior Publication US 2009/0033421 A1, Feb. 05, 2009 | ||
| Int. Cl. H03K 19/094 (2006.01); H03K 19/0175 (2006.01) | ||
| U.S. Cl. 326—84 [326/115; 326/127; 330/102; 330/253] | 16 Claims |
| 1. A differential input driver circuit (10, 50) comprising:
a first transistor (Q0) having a first current handling terminal (24, 64) coupled to receive a first differential input signal (In+), a second current handling terminal (16, 56) coupled to receive a first current (I0) and a control terminal (20, 60), the second current handling terminal providing a first differential output signal (Vo+);
a first resistor (R0) coupled between the first current handling terminal (24, 64) of the first transistor and a first power supply voltage (14, 52);
a second transistor (Q3) having a first current handling terminal (26, 66) coupled to receive a second differential input signal (In−), a second current handling terminal (18, 58) coupled to receive a second current (I3) and a control terminal (22, 62), the second current handling terminal providing a second differential output signal (Vo−);
a second resistor (R1) coupled between the first current handling terminal (26, 66) of the second transistor and the first power supply voltage;
a third transistor (Q1) having a first current handling terminal coupled to the first current handling terminal (26, 66) of the second transistor (Q3), and a control terminal connected to the second current handling terminal (20, 60) and to the control terminal of the first transistor and receiving a third current (I1);
a fourth transistor (Q2) having a first current handling terminal coupled to the first current handling terminal (24, 64) of the first transistor, and a control terminal connected to the second current handling terminal (22, 62) and to the control terminal of the second transistor and receiving a fourth current (I2),
wherein the first, second, third and fourth transistors are all of a first polarity type.
|