| US 7,501,837 B2 | ||
| Test structure and method for detecting charge effects during semiconductor processing using a delayed inversion point technique | ||
| Ming-Chang Kuo, Changhua (Taiwan); Ming-Hsiu Lee, Hsinchu (Taiwan); and Chao-I Wu, Tainan (Taiwan) | ||
| Assigned to Macronix International Co. Ltd., (Taiwan) | ||
| Filed on Apr. 10, 2006, as Appl. No. 11/279,224. | ||
| Prior Publication US 2007/0236237 A1, Oct. 11, 2007 | ||
| Int. Cl. G01R 31/302 (2006.01) | ||
| U.S. Cl. 324—750 [324/158.1] | 14 Claims |
| 1. A method for monitoring a charge status for a test structure formed on a silicon substrate that results from a semiconductor
processing step, the method comprising:
performing a first CV measurement on the test structure to generate a first CV curve;
subjecting the test structure to the semiconductor processing step;
performing a second CV measurement on the test structure to generate a second CV curve;
detecting whether there is a shift between the first and the second CV curves; and
when there is not a shift, monitoring the charge status for the test structure based at least in part on delayed inversion
point information.
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