| US 7,501,336 B2 | ||
| Metal gate device with reduced oxidation of a high-k gate dielectric | ||
| Brian S. Doyle, Portland, Oreg. (US); Jack Kavalieros, Portland, Oreg. (US); Justin K. Brask, Portland, Oreg. (US); Matthew V. Mertz, Portland, Oreg. (US); Mark L. Doczy, Beaverton, Oreg. (US); Suman Datta, Beaverton, Oreg. (US); and Robert S. Chau, Beaverton, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Jun. 21, 2005, as Appl. No. 11/158,621. | ||
| Prior Publication US 2006/0284271 A1, Dec. 21, 2006 | ||
| Int. Cl. H01L 21/3205 (2006.01); H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—591 [257/E21.111] | 13 Claims |
| 1. A method for making a semiconductor device, comprising:
forming a high-k gate dielectric layer on a semiconductor substrate;
forming a metal gate electrode on the high-k gate dielectric layer, the metal gate electrode having a first side and a second
side;
forming a first set of spacers on the first and second sides of the metal gate electrode, wherein the first set of spacers
is substantially free of oxygen; and
forming a capping layer that is substantially free of oxygen on a top surface of the substrate layer, sides of the first set
of spacers, and a top surface of the metal gate electrode.
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