| US 7,501,324 B2 | ||
| Advanced CMOS using super steep retrograde wells | ||
| Jeffrey A. Babcock, Richardson, Tex. (US); Angelo Pinto, Allen, Tex. (US); Scott Balster, Dallas, Tex. (US); Alfred Haeusler, Freising (Germany); and Gregory E. Howard, Dallas, Tex. (US) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on Apr. 27, 2006, as Appl. No. 11/380,602. | ||
| Application 11/380602 is a division of application No. 09/948856, filed on Sep. 07, 2001, granted, now 7,064,399. | ||
| Claims priority of provisional application 60/232913, filed on Sep. 15, 2000. | ||
| Prior Publication US 2006/0197158 A1, Sep. 07, 2006 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—289 [438/527] | 9 Claims |
| 1. A method of forming a super steep retrograde well (SSRW), comprising:
providing a semiconductor substrate with an upper surface;
performing a plurality of implants into the silicon substrate to form a retrograde well region; and
implanting carbon into said substrate to form a carbon capping layer above at least a portion of said retrograde well region
according to a device threshold voltage and at a first distance from the upper surface of the silicon surface.
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