US 7,501,297 B2
Thin film transistor array panel and manufacturing method thereof
Jang-Soo Kim, Gyeonggi-do (Korea, Republic of); Soo-Jin Kim, Gyeonggi-do (Korea, Republic of); Kyoung-Tai Han, Gyeonggi-do (Korea, Republic of); Hee-Hwan Choe, Incheon-si (Korea, Republic of); and Joo-Han Kim, Gyeonggi-do (Korea, Republic of)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of)
Filed on Jan. 20, 2006, as Appl. No. 11/336,087.
Claims priority of application No. 10-2005-0005306 (KR), filed on Jan. 20, 2005.
Prior Publication US 2006/0160282 A1, Jul. 20, 2006
Int. Cl. H01L 21/00 (2006.01)
U.S. Cl. 438—30  [438/148; 438/149; 438/151; 438/157; 438/193; 438/283; 438/587; 438/FOR.184; 438/FOR.201] 16 Claims
OG exemplary drawing
 
1. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate line on a substrate;
forming a first insulating layer on the gate line;
forming a semiconductor layer on the flint insulating layer;
forming a conductive layer;
forming a data line and a drain electrode from the conductive layer and on the semiconductor Layer;
depositing passivation layer on the data line and the drain electrode;
forming a photoresist on the passivation layer;
etching the passivation layer and the first insulating layer using the photoresist as a mask to expose portions of the conductive layer and at least a part of the substrate;
partially removing an exposed portion of the conductive layer;
depositing a conductive film on the photoresist, and exposed portions of the conductive layer and the substrate; and
removing the photoresist and the conductive film deposited on the photoresist, to form a pixel electrode connected to the exposed portion of the drain electrode.