	US 7,501,212 B2
	Method for generating design rules for a lithographic mask design that includes long range flare effects
Kafai Lai, Poughkeepsie, N.Y. (US); Chieh-Yu Lin, Hopewell Junction, N.Y. (US); Nayak Jawahar, Wappingers Falls, N.Y. (US); and Mukherjee Maharaj, Wappingers Falls, N.Y. (US)
Assigned to International Business Machines Corporation, Armonk, N.Y. (US)
Filed on Jan. 05, 2005, as Appl. No. 11/29,884.
Prior Publication US 2006/0150131 A1, Jul. 06, 2006
Int. Cl. G03F 9/00 (2006.01)

U.S. Cl. 430—5 [716/19; 716/21]

20 Claims

1. A method for generating rules for a mask layout design of a Very Large Scale Integrated Circuit (VLSI) chip, said chip layout consisting of a plurality of layers, each of said layer having predetermined critical dimensions, predefined optical lithography process and at least one mask, said critical dimensions having predetermined tolerances, the method comprising:

a. forming at least one shape for said at least one mask and determining whether there is at least one region of the mask affecting said critical dimensions;

b. if at least one of said regions is found, determining a maximum energy emanating from said at least one region that maintains the critical dimension of said shape within said tolerance;

c. creating a corresponding rule for said region that characterizes an actual energy emanating from said region is at most equal to said maximum energy; and

d. constructing the chip layout with said rule assigned to said region.