| US 7,500,148 B2 | ||
| Test apparatus and testing method | ||
| Kiyoshi Murata, Tokyo (Japan) | ||
| Assigned to Advantest Corporation, Tokyo (Japan) | ||
| Filed on Jul. 13, 2005, as Appl. No. 11/180,972. | ||
| Application 11/180972 is a continuation of application No. PCT/JP2005/012833, filed on Jul. 12, 2005. | ||
| Claims priority of application No. 2004-242993 (JP), filed on Aug. 23, 2004. | ||
| Prior Publication US 2006/0190794 A1, Aug. 24, 2006 | ||
| Int. Cl. G06F 11/00 (2006.01) | ||
| U.S. Cl. 714—32 [714/742; 714/732] | 10 Claims |
| 1. A testing apparatus that tests a device under test, comprising:
a command executing unit operable to sequentially execute commands included in a test program for the device under test every
command cycle;
a test pattern memory operable to store pattern sequence and pattern length identifying information corresponding to each
of the commands, the pattern length identifying information identifying a pattern length of a test pattern sequence that is
output during a command cycle period for executing each command;
a test pattern memory reading unit operable to read a test pattern sequence having a length corresponding to the pattern length
identifying information stored on said test pattern memory in association with one command from said test pattern memory when
the one command is executed; and
a test pattern outputting unit operable to output the test pattern sequence read by said test pattern memory reading unit
in association with the one command to a terminal of the device under test during a command cycle period for executing the
one command.
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