a processor having a processor architecture that provides speculative execution of machine instructions and exposes said speculative execution to program control through at least one machine instruction; and

a memory coupled with the processor, the memory embodying information indicative of instructions, including the at least one machine instruction, that result in synchronization between parallel processes when performed by the processor with detection of mis-speculation;

wherein performance of the instructions by the processor comprises performing a speculative read-modify-write to a lock variable associated with a critical section and ending speculation before performing the critical section;

wherein the at least one machine instruction comprises:

a speculative execution instruction that takes first and second operands, behaves as a no-op if a memory location indicated by the first operand contains a first value, causes the processor to speculatively execute additional instructions if the memory location contains a second value, and causes the processor to start executing instructions from an address indicated by the second operand if a mis-speculation occurs; and

a speculation termination instruction that causes the processor to begin retiring the additional instructions if the additional instructions have been speculatively executed.