| US 7,500,029 B2 | ||
| Maximal length packets | ||
| Sivakumar Radhakrishnan, Portland, Oreg. (US); Siva Balasubramanian, Chandler, Ariz. (US); Sin S. Tan, Portland, Oreg. (US); and Suneeta Sah, Portland, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Oct. 29, 2004, as Appl. No. 10/977,230. | ||
| Prior Publication US 2006/0168384 A1, Jul. 27, 2006 | ||
| Int. Cl. G06F 3/00 (2006.01) | ||
| U.S. Cl. 710—33 [710/30] | 26 Claims |
| 1. A method of combining outbound write transactions in a chip coupled between a processor and an input/output (I/O) device
comprising:
receiving, at the chip, outbound write transactions of write data sent from the processor to the (I/O) device;
combining, within a write combining storage area on the chip, the outbound write transactions of the write data into a packet
until a maximum length of the write data is obtained;
receiving a flush request signal from the I/O device requesting a flush of the packet stored in the write combining storage
area; and
in response to receiving the flush request signal from the I/O device, repeatedly detecting whether the packet stored in the
write combining storage area has grown to the maximum length packet of write data; and
flushing the requested packet to the I/O device over a bus whenever the packet is determined to have grown to the maximum
length, each maximum length packet being a packet of maximum payload of the write data that can be formulated within the write
combining storage area while adhering to packet protocol rules for the bus.
|