| US 7,499,516 B2 | ||
| Methods and apparatus for interface buffer management and clock compensation in data transfers | ||
| Brijesh Mani Tripathi, Whitehall, Pa. (US) | ||
| Assigned to Agere Systems, Inc., Allentown, Pa. (US) | ||
| Filed on Nov. 19, 2004, as Appl. No. 10/993,542. | ||
| Prior Publication US 2006/0109929 A1, May 25, 2006 | ||
| Int. Cl. H04L 7/00 (2006.01); H04L 25/00 (2006.01); H04L 25/40 (2006.01) | ||
| U.S. Cl. 375—372 [375/371; 375/354; 372/141] | 14 Claims |
| 1. An apparatus comprising:
a look ahead circuit for detecting a clock compensation pattern for a data channel and generating a clock compensation indicator
signal;
a first in first out (FIFO) buffer with a data input and a data output, the FIFO buffer holding a plurality of accessible
data elements, each data element having an associated clock compensation indicator bit derived from the clock compensation
indicator signal for use in clock compensation of data transfers;
a system application clock;
a FIFO read circuit using the system application clock, the FIFO read circuit for reading a data element and the clock compensation
indicator bit from the FIFO buffer and generating an almost empty signal when there is one data element left in the FIFO buffer;
a clock recovered from the data channel; and
a FIFO write circuit using the recovered clock for writing a data element into the FIFO buffer and writing the clock compensation
indicator signal into the clock compensation indicator bit in the FIFO buffer, wherein the FIFO write circuit skips the writing
of at least a subset of the clock compensation pattern into the FIFO buffer after a clock compensation pattern has been detected.
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