| US 7,499,464 B2 | ||
| Buffered crossbar switch with a linear buffer to port relationship that supports cells and packets of variable size | ||
| Robert Ayrapetian, 17490 Calle Mazatan, Morgan Hill, Calif. 95037 (US); Edward Ayrapetian, 17490 Calle Mazatan, Morgan Hill, Calif. 95037 (US); and Serob Douvalian, 17490 Calle Mazatan, Morgan Hill, Calif. 95037 (US) | ||
| Filed on Apr. 06, 2006, as Appl. No. 11/400,367. | ||
| Claims priority of provisional application 60/669028, filed on Apr. 06, 2005. | ||
| Prior Publication US 2006/0256783 A1, Nov. 16, 2006 | ||
| Int. Cl. H04L 12/28 (2006.01) | ||
| U.S. Cl. 370—419 [370/412; 370/428; 710/52] | 6 Claims |
| 1. For use in a network system having a line card that generates data packets, a buffered crossbar switch having multiple
buffers and a linear buffer to port relationship, where the number of buffers is less than the number of ports squared, where
the number of buffers of the switch is linearly related to the number of ports of the switch, comprising:
an internal buffer address decoder and control module, where the decoder is configured to receive address information from
a line card scheduler and to decode the address information and generate a decoded address and wherein the control module
negotiates the transfer of data from the line card to internal buffers;
an input configured to receive data packets from the line card and to deserialize the data packets to generate a deserialized
output; and
a plurality of buffer structures, one for each port, each configured to receive a deserialized output from the input and to
control an internal buffer system, where the each buffer structure includes
a buffer read/write control configured to receive decoded addresses from the internal buffer address decoder and negotiate
data transfers with the address decoder based on an internal buffer status;
a plurality of multiplexers that route the received deserialized data from the input control by the buffer read/write control;
a plurality of buffers, where each buffer is configured to receive data packets from the an associated multiplexer and to
send a report signal, indicating whether the buffer is full, to the buffer read/write control; and
a central buffer configured to receive outputs from the plurality of buffers and to generate an output.
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