a turbo decoder for decoding the packet data;

a dualized buffer for storing the decoded packet data, and outputting packet data upon receiving a read request,

a buffer controller for receiving a decoding done signal from the turbo decoder, and generating an interrupt signal and a read address for reading data stored in the dualized buffer; and

a processor for reading data stored in the dualized buffer according to the read address upon receiving the interrupt signal from the buffer controller;

wherein the buffer controller comprises:

a page buffer selector for receiving a system time signal of a receiver, selceting one dualized buffer according to a 1-slot delay response mode determined from the system time, and determining a given page of the selected buffer;

a stop position selector for receiving the system time signal and a decoding clock, and generating a stop position signal that can be randomly set in one slot;

a flag generator being cleared according to the system time of the receiver, for outputting a flag according to a turbo decoder enable signal of the packet data;

a buffer selector for receiving a signal of the flag generator, an output signal of the stop position selector, and the turbo decoder enable signal, and selecting one of the dualized areas according to a 2-slot delay response mode;

a page selector for selecting a page of the selected area according to the 2-slot delay response mode; and

an interrupt controller for generating an interrupt signal by receiving signals from the page buffer selector, the buffer selector and the page selector, and buffer status signals from the duslized area buffer.