| US 7,499,360 B2 | ||
| Flash/dynamic random access memory field programmable gate array | ||
| John McCollum, Saratoga, Calif. (US); Vidya Bellippady, Cupertino, Calif. (US); and Gregory Bakker, San Jose, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Jan. 03, 2007, as Appl. No. 11/619,547. | ||
| Application 11/619547 is a continuation of application No. 11/484244, filed on Jul. 10, 2006, granted, now 7,187,610. | ||
| Application 11/484244 is a continuation of application No. 11/113286, filed on Apr. 21, 2005, granted, now 7,120,079, filed on Oct. 10, 2006. | ||
| Application 11/113286 is a continuation of application No. 10/623111, filed on Jul. 17, 2003, granted, now 6,891,769, filed on May 10, 2005. | ||
| Prior Publication US 2007/0104009 A1, May 10, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—222 [365/189.01] | 9 Claims |
| 1. A method for interconnecting two nodes in an integrated circuit device comprising:
storing a charge representing an on-status bit on a gate capacitance of a switching transistor coupled between the two nodes;
and
periodically refreshing said charge, wherein periodically refreshing said charge is performed at a periodic interval that
is a function of temperature of a die on which said circuit is disposed and comprises periodically coupling a voltage representing
said on-status bit to said gate capacitance of said switching transistor through a refresh transistor.
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